{"id":26,"date":"2021-10-13T14:39:37","date_gmt":"2021-10-13T14:39:37","guid":{"rendered":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/?p=26"},"modified":"2021-10-13T14:41:05","modified_gmt":"2021-10-13T14:41:05","slug":"display-engine","status":"publish","type":"post","link":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/2021\/10\/13\/display-engine\/","title":{"rendered":"Display Engine"},"content":{"rendered":"\n<p>The first deliverable for this project was creating a display engine that could properly drive a VGA display at 800&#215;600 resolution. In order to do this, a Vsync and Hsync signal must be generated that matches VGA specifications. <\/p>\n\n\n\n<p>Using a pixel clock of 40Mhz an Hsync signal must be low for 840 pixel clock periods, high for the next 128 periods, low for the following 88 periods, and repeating. Using a module to count these periods, we were able to recreate this Hsync signal to match this criteria.<\/p>\n\n\n\n<p>To create the Vertical Sync signal, we used the horizontal counter to increment a vertical counter on every horizontal counter reset to indicate a new line. Using this counter the Vsync signal will be low for the first 601 vertical lines, high for 4 lines, low for 23 lines, and repeat.<\/p>\n\n\n\n<p>Outputting these signals to a VGA display yields the following results:<\/p>\n\n\n\n<figure class=\"wp-block-image size-full is-resized\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-content\/uploads\/sites\/192\/2021\/10\/IMG_0027-1.jpg\" alt=\"\" class=\"wp-image-28\" width=\"535\" height=\"499\" srcset=\"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-content\/uploads\/sites\/192\/2021\/10\/IMG_0027-1.jpg 352w, https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-content\/uploads\/sites\/192\/2021\/10\/IMG_0027-1-300x280.jpg 300w\" sizes=\"auto, (max-width: 535px) 100vw, 535px\" \/><\/figure>\n","protected":false},"excerpt":{"rendered":"<p>The first deliverable for this project was creating a display engine that could properly drive a VGA display at 800&#215;600 resolution. In order to do this, a Vsync and Hsync signal must be generated that matches VGA specifications. Using a pixel clock of 40Mhz an Hsync signal must be low for 840 pixel clock periods, &hellip; <a href=\"https:\/\/engprojects.tcnj.edu\/3d-fpga\/2021\/10\/13\/display-engine\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Display Engine<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":373,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[4],"tags":[],"class_list":["post-26","post","type-post","status-publish","format-standard","hentry","category-projectupdates"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/posts\/26","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/users\/373"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/comments?post=26"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/posts\/26\/revisions"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/media?parent=26"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/categories?post=26"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/3d-fpga\/wp-json\/wp\/v2\/tags?post=26"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}