As The College of New Jersey’s first senior project to perform a physical design for an Application Specific Integrated Circuit (ASIC), we will be working to convert a previous year’s senior project files from Verilog into a physical chip. These files contain code that simulates an advanced 512-tap finite impulse response (FIR) digital audio filter with signed 16-bit fully programmable coefficients, programmable via I2C as a slave device. This chip is capable of delivering two channels of audio with 16-bits per channel, up to 48kHz sampling clock, and audio streaming through I2S.

The project will make use of Global Foundries’ 8RF 130nm CMOS process to fabricate the chip, a service made available to students at no charge. Verilog files will be run through Cadence Synopsys to generate a gate-level netlist by translating high-level language into primitive AND gates, OR gates, and flip-flops. From here, the files will be converted into a form that Mentor’s Pyxis software can accept in order for floor planning, clock and power routing, and bond pad placement to be performed. Finally, Mentor will be used to perform static timing analyses to detect propagation delays as well as setup/hold time violations.

The team would like to thank Dr. Pearlstein and Dr. Hernandez for their extensive help throughout the project.