{"id":34,"date":"2019-09-12T18:55:55","date_gmt":"2019-09-12T18:55:55","guid":{"rendered":"http:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/?page_id=34"},"modified":"2019-12-02T15:08:17","modified_gmt":"2019-12-02T15:08:17","slug":"timeline","status":"publish","type":"page","link":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/timeline\/","title":{"rendered":"Timeline"},"content":{"rendered":"

<\/p>\n

Semester 1 :<\/p>\n

<\/p>\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
Name<\/th>\nDuration<\/th>\nActual Start<\/th>\nFinish<\/th>\nPercent Complete<\/th>\n<\/tr>\n
Maintain Website<\/td>\n50 days<\/td>\n8\/9\/19<\/td>\n10\/17\/19<\/td>\n30%<\/td>\n<\/tr>\n
Documentation<\/td>\n50 days<\/td>\n8\/15\/19<\/td>\n10\/23\/19<\/td>\n50%<\/td>\n<\/tr>\n
Software Architecture<\/td>\n50 days<\/td>\n8\/15\/19<\/td>\n10\/23\/19<\/td>\n50%<\/td>\n<\/tr>\n
C UART<\/td>\n50 days<\/td>\n8\/19\/19<\/td>\n10\/25\/19<\/td>\n50%<\/td>\n<\/tr>\n
Image and Kernel Storage<\/td>\n3 days<\/td>\n8\/28\/19<\/td>\n8\/30\/19<\/td>\n100%<\/td>\n<\/tr>\n
Verification and Debugging<\/td>\n30 days<\/td>\n9\/2\/19<\/td>\n10\/11\/19<\/td>\n0%<\/td>\n<\/tr>\n
C Image Loader<\/td>\n35 days<\/td>\n8\/15\/19<\/td>\n10\/2\/19<\/td>\n20%<\/td>\n<\/tr>\n
C Image and Kernel Preprocessor<\/td>\n40 days<\/td>\n8\/19\/19<\/td>\n10\/11\/19<\/td>\n20%<\/td>\n<\/tr>\n
C UART Master<\/td>\n40 days<\/td>\n8\/26\/19<\/td>\n10\/18\/19<\/td>\n50%<\/td>\n<\/tr>\n
Present Data<\/td>\n40 days<\/td>\n8\/9\/19<\/td>\n10\/3\/19<\/td>\n30%<\/td>\n<\/tr>\n
Develop Architecture in C Program<\/td>\n40 days<\/td>\n9\/2\/19<\/td>\n10\/25\/19<\/td>\n5%<\/td>\n<\/tr>\n
C Image Restitch<\/td>\n50 days<\/td>\n8\/26\/19<\/td>\n11\/1\/19<\/td>\n0%<\/td>\n<\/tr>\n
VHDL Data Master<\/td>\n50 days<\/td>\n9\/20\/19<\/td>\n11\/28\/19<\/td>\n20%<\/td>\n<\/tr>\n
VHDL Data Master Testing<\/td>\n20 days<\/td>\n9\/20\/19<\/td>\n10\/17\/19<\/td>\n0%<\/td>\n<\/tr>\n
Testing and Redesign<\/td>\n20 days<\/td>\n10\/15\/19<\/td>\n11\/11\/19<\/td>\n0%<\/td>\n<\/tr>\n
Documentation<\/td>\n70 days<\/td>\n9\/5\/19<\/td>\n12\/11\/19<\/td>\n0%<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n\n\n

FPGA Design<\/h2>\n\n\n\n
\"\"\/<\/figure>\n\n\n\n

Software Design<\/h2>\n\n\n\n
\"\"\/<\/figure>\n\n\n\n

Budget Chart<\/h2>\n\n\n\n
\"\"<\/figure>\n","protected":false},"excerpt":{"rendered":"

Semester 1 : Name Duration Actual Start Finish Percent Complete Maintain Website 50 days 8\/9\/19 10\/17\/19 30% Documentation 50 days 8\/15\/19 10\/23\/19 50% Software Architecture 50 days 8\/15\/19 10\/23\/19 50% C UART 50 days 8\/19\/19 10\/25\/19 50% Image and Kernel Storage 3 days 8\/28\/19 8\/30\/19 100% Verification and Debugging 30 days 9\/2\/19 10\/11\/19 0% C … <\/p>\n

Continue reading “Timeline”<\/span><\/a><\/p>\n","protected":false},"author":197,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-34","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/pages\/34","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/users\/197"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/comments?post=34"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/pages\/34\/revisions"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/media?parent=34"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}