{"id":69,"date":"2019-11-13T16:33:11","date_gmt":"2019-11-13T16:33:11","guid":{"rendered":"http:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/?page_id=69"},"modified":"2020-03-30T17:03:14","modified_gmt":"2020-03-30T17:03:14","slug":"project-overview","status":"publish","type":"page","link":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/project-overview\/","title":{"rendered":"Project Overview"},"content":{"rendered":"\n<p><\/p>\n\n\n<p>DCNNs are increasing in prevalence; however, their high computational load makes them difficult for real-time. FPGAs are used to parallelize and accelerate this load, which is why they are the ideal hardware to use for the design of a convolutional neural network.<\/p>\n<p>&nbsp;<\/p>\n\n\n<p><h3>Project Goals<\/h3><\/p>\n\n\n\n<p>A&nbsp;system for accelerating convolutions used for image processing and filtering, or implementation of a convolutional neural network. Hardware based acceleration, supporting flexible zero padding.<\/p>\n\n\n\n<ul class=\"wp-block-list\"><li>Have an FPGA do an on-demand image convolution when the PC tells it to&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;<\/li><li>Build a convolution hardware framework using Verilog, then using (low level) C have to PC send commands\/image data to the FPGA<\/li><li>Explore the implementation of neural networks in FPGAs<ul><li>Map out resource usage\/latency for deep neural network architectures and hyperparameters<ul><li>Latency refers to the total time (typically expressed in units of \u201cclocks\u201d), required for a single iteration of the algorithm to complete<\/li><\/ul><\/li><li>Demonstrate deep learning techniques in FPGA applications<\/li><\/ul><\/li><\/ul>\n","protected":false},"excerpt":{"rendered":"<p>DCNNs are increasing in prevalence; however, their high computational load makes them difficult for real-time. FPGAs are used to parallelize and accelerate this load, which is why they are the ideal hardware to use for the design of a convolutional neural network. &nbsp; Project Goals A&nbsp;system for accelerating convolutions used for image processing and filtering, &hellip; <\/p>\n<p class=\"link-more\"><a href=\"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/project-overview\/\" class=\"more-link\">Continue reading<span class=\"screen-reader-text\"> &#8220;Project Overview&#8221;<\/span><\/a><\/p>\n","protected":false},"author":36,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-69","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/pages\/69","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/users\/36"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/comments?post=69"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/pages\/69\/revisions"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/media?parent=69"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}