{"id":1,"date":"2019-08-19T14:16:48","date_gmt":"2019-08-19T14:16:48","guid":{"rendered":"http:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/?p=1"},"modified":"2020-03-30T17:02:53","modified_gmt":"2020-03-30T17:02:53","slug":"hello-world","status":"publish","type":"post","link":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/2019\/08\/19\/hello-world\/","title":{"rendered":"Convolutional Neural Network Acceleration Hardware"},"content":{"rendered":"\n

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Project Overview<\/h1>\n<\/header>\n
Deep Convolutional Neural Networks (DCNNs) have made significant progress in approaching a wide range of problems in the general area of computer vision. However, they generally require enormous computational resources and are therefore difficult to deploy in real-time systems. To address this problem, we designed a system for accelerating the core operations required by DCNNs, by using a low-cost Field Programmable Gate Array (FPGA) platform. We designed an end-to-end accelerator platform, including a PC running Linux, an FPGA board and PC-to-FPGA communication via serial data (over USB). We designed a hardwired convolution processor using custom fixed-point multipliers, and a software handler for sending and reconstructing images. Using custom Verilog\/VHDL RTL descriptions and C++ software, we aim to exploit the parallelism inherent to FPGAs for high-speed acceleration.<\/span><\/p>\n\n\n\n
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Project Overview Deep Convolutional Neural Networks (DCNNs) have made significant progress in approaching a wide range of problems in the general area of computer vision. However, they generally require enormous computational resources and are therefore difficult to deploy in real-time systems. To address this problem, we designed a system for accelerating the core operations required … <\/p>\n
Continue reading “Convolutional Neural Network Acceleration Hardware”<\/span><\/a><\/p>\n","protected":false},"author":20,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"ngg_post_thumbnail":0,"footnotes":""},"categories":[1],"tags":[],"class_list":["post-1","post","type-post","status-publish","format-standard","hentry","category-uncategorized"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/posts\/1","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/users\/20"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/comments?post=1"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/posts\/1\/revisions"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/media?parent=1"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/categories?post=1"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/neuralnetaccelerator\/wp-json\/wp\/v2\/tags?post=1"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}