{"id":133,"date":"2015-10-13T23:27:11","date_gmt":"2015-10-13T23:27:11","guid":{"rendered":"http:\/\/tcnjchip.pages.tcnj.edu\/?page_id=133"},"modified":"2015-10-13T23:27:11","modified_gmt":"2015-10-13T23:27:11","slug":"system-design","status":"publish","type":"page","link":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/project\/system-design\/","title":{"rendered":"System Design"},"content":{"rendered":"<p style=\"text-align: justify\">System design has been fully completed and involved the use of CORE 9 to document the requirements of the project and each project member creating\u00a0a block\u00a0document that detailed\u00a0the specifics of their module.<\/p>\n<p><strong>CORE 9:<\/strong><\/p>\n<ul>\n<li>Documented components, functions, and requirements of chip<\/li>\n<li>Used these requirements to generate a detailed schedule and\u00a0Gantt chart in Microsoft Project<\/li>\n<\/ul>\n<p><strong>Module\/Block Document Details:<\/strong><\/p>\n<ul>\n<li>Interfaces\n<ul>\n<li>Interface signal listing and naming<\/li>\n<\/ul>\n<\/li>\n<li>Functional Requirements\n<ul>\n<li>Data Plane Requirements\n<ul>\n<li>What algorithm will be used?<\/li>\n<\/ul>\n<\/li>\n<li>Control Plane Requirements\n<ul>\n<li>Protocols for sending and receiving data<\/li>\n<li>Buffer sizing<\/li>\n<li>Is overflow\/underflow possible?<\/li>\n<\/ul>\n<\/li>\n<li>Control and Status Interface Bit Descriptions\n<ul>\n<li>Control bit settings<\/li>\n<li>Status bits<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<li>Micro-Architecture\n<ul>\n<li>Specify sub-blocks<\/li>\n<li>Sub-block interfaces<\/li>\n<\/ul>\n<\/li>\n<li>Design\n<ul>\n<li>Low-level design description<\/li>\n<li>How many gates and flip flops?<\/li>\n<li>How fast can the design run?<\/li>\n<\/ul>\n<\/li>\n<li>Verification\n<ul>\n<li>Testbench\n<ul>\n<li>Block diagram<\/li>\n<li>How test cases will be designed?<\/li>\n<li>How stimulus will be created?<\/li>\n<li>How will responses be judged?<\/li>\n<\/ul>\n<\/li>\n<li>Test Plan\n<ul>\n<li>Describe each test case<\/li>\n<li>Explain how test suite aims to achieve 100% coverage that the block meets the requirements<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n<p><strong>Top-Level Chip Design:<\/strong><\/p>\n<p><a href=\"http:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/10\/Chip-Drawing.png\" rel=\"attachment wp-att-205\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-full wp-image-205\" src=\"http:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/10\/Chip-Drawing.png\" alt=\"Chip Drawing\" width=\"1023\" height=\"710\" \/><\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>System design has been fully completed and involved the use of CORE 9 to document the requirements of the project and each project member creating\u00a0a block\u00a0document that detailed\u00a0the specifics of their module. CORE 9: Documented components, functions, and requirements of chip Used these requirements to generate a detailed schedule and\u00a0Gantt chart in Microsoft Project Module\/Block &hellip; <a href=\"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/project\/system-design\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">System Design<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":126,"featured_media":0,"parent":45,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-133","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/133","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/users\/126"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/comments?post=133"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/133\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/45"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/media?parent=133"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}