{"id":141,"date":"2015-10-13T23:54:02","date_gmt":"2015-10-13T23:54:02","guid":{"rendered":"http:\/\/tcnjchip.pages.tcnj.edu\/?page_id=141"},"modified":"2015-10-13T23:54:02","modified_gmt":"2015-10-13T23:54:02","slug":"register-transfer-level-rtl-design","status":"publish","type":"page","link":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/project\/register-transfer-level-rtl-design\/","title":{"rendered":"RTL Design"},"content":{"rendered":"<p style=\"text-align: justify\">The register-transfer level (RTL) design is composed of 5 modules. The modules are for the I2C Slave interface (i2c_slave.v), I2S input interface (i2si.v), I2S output interface (i2so.v), register (register.v), and filter (filter.v). All modules are connected in the top-level module named chip.v. All modules have been coded and tested.<\/p>\n<ul>\n<li style=\"text-align: justify\">i2c.v (100%)<\/li>\n<li style=\"text-align: justify\">i2c_deserializer.v (100%)<\/li>\n<li style=\"text-align: justify\">i2c_sequencer.v (100%)<\/li>\n<li style=\"text-align: justify\">i2c_serializer.v (100%)<\/li>\n<\/ul>\n<p style=\"text-align: justify\"><b>i2s_in.v (100%):\u00a0<\/b><\/p>\n<ul>\n<li style=\"text-align: justify\">i2s_in.v (100%)<\/li>\n<li style=\"text-align: justify\">i2si_deserializer.v (100%)<\/li>\n<li style=\"text-align: justify\">i2si_bist_gen.v (100%)<\/li>\n<li style=\"text-align: justify\">i2si_fifo.v (100%)<\/li>\n<li style=\"text-align: justify\">i2si_mux (100%)<\/li>\n<\/ul>\n<p style=\"text-align: justify\"><strong>i2s_out.v (100%):<\/strong><\/p>\n<ul>\n<li style=\"text-align: justify\">i2s_out.v (100%)<\/li>\n<li style=\"text-align: justify\">i2so_serializer.v (100%)<\/li>\n<li style=\"text-align: justify\">i2so_fifo.v (100%)<\/li>\n<\/ul>\n<p style=\"text-align: justify\"><strong>chip_reg.v (100%):<\/strong><\/p>\n<ul>\n<li style=\"text-align: justify\">register.v (100%)<\/li>\n<li style=\"text-align: justify\">register_trig_gen.v (100%)<\/li>\n<\/ul>\n<p style=\"text-align: justify\"><strong>filter.v (100%):<\/strong><\/p>\n<ul>\n<li style=\"text-align: justify\">filter.v (100%)<\/li>\n<li style=\"text-align: justify\">filter_convolution.v (100%)<\/li>\n<li style=\"text-align: justify\">filter_accumulator.v (100%)<\/li>\n<li style=\"text-align: justify\">filter_round_shift_clip.v (100%)<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>The register-transfer level (RTL) design is composed of 5 modules. The modules are for the I2C Slave interface (i2c_slave.v), I2S input interface (i2si.v), I2S output interface (i2so.v), register (register.v), and filter (filter.v). All modules are connected in the top-level module named chip.v. All modules have been coded and tested. i2c.v (100%) i2c_deserializer.v (100%) i2c_sequencer.v (100%) &hellip; <a href=\"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/project\/register-transfer-level-rtl-design\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">RTL Design<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":126,"featured_media":0,"parent":45,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-141","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/141","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/users\/126"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/comments?post=141"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/141\/revisions"}],"up":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/45"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/media?parent=141"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}