{"id":234,"date":"2015-09-02T19:21:41","date_gmt":"2015-09-02T19:21:41","guid":{"rendered":"http:\/\/engineeringseniorproject.pages.tcnj.edu\/?page_id=2"},"modified":"2015-09-02T19:21:41","modified_gmt":"2015-09-02T19:21:41","slug":"sample-page-2","status":"publish","type":"page","link":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/sample-page-2\/","title":{"rendered":"Project Home"},"content":{"rendered":"<p><a href=\"http:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/09\/asic.png\"><img loading=\"lazy\" decoding=\"async\" class=\"aligncenter size-large wp-image-193\" src=\"http:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/09\/asic-1024x1009.png\" alt=\"asic\" width=\"474\" height=\"467\" srcset=\"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/09\/asic-1024x1009.png 1024w, https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/09\/asic-300x296.png 300w, https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/09\/asic-768x757.png 768w, https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-content\/uploads\/sites\/79\/2015\/09\/asic.png 1058w\" sizes=\"auto, (max-width: 474px) 100vw, 474px\" \/><\/a><\/p>\n<p style=\"text-align: justify\"><strong>Project Proposal:\u00a0<\/strong>The goal of this project is to gain experience in VLSI design by designing a chip that will process digital streaming audio data. More specifically, we will implement a 512-tap digital finite impulse response (FIR) filter, which will be applied to an input stream in order to create an output stream. We used the I2C protocol to allow a host to control the chip and the serial I2S protocol for transferring digital audio streams in and out.<\/p>\n<p style=\"text-align: justify\">Our hardware design was represented using Verilog register-transfer level (RTL) code. Development has been done using Xilinx ISE Design Suite 14.7. Test-benches were also designed and implemented using Verilog. The end goal of the project is to implement the design on a field-programmable gate array (FPGA). We will bring up our FPGA design with a realistic environment including an audio source, audio sink, and a microcontroller for reading and writing registers. We also plan to send a simple CMOS integrated circuit design for fabrication by MOSIS that will help us gain experience in physical chip design and prepare future groups to fabricate our full design.<\/p>\n<p><strong>Current Status:\u00a0<\/strong>Complete<\/p>\n","protected":false},"excerpt":{"rendered":"<p>Project Proposal:\u00a0The goal of this project is to gain experience in VLSI design by designing a chip that will process digital streaming audio data. More specifically, we will implement a 512-tap digital finite impulse response (FIR) filter, which will be applied to an input stream in order to create an output stream. We used the &hellip; <a href=\"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/sample-page-2\/\" class=\"more-link\">Continue reading <span class=\"screen-reader-text\">Project Home<\/span> <span class=\"meta-nav\">&rarr;<\/span><\/a><\/p>\n","protected":false},"author":15,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"ngg_post_thumbnail":0,"footnotes":""},"class_list":["post-234","page","type-page","status-publish","hentry"],"_links":{"self":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/234","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/users\/15"}],"replies":[{"embeddable":true,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/comments?post=234"}],"version-history":[{"count":0,"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/pages\/234\/revisions"}],"wp:attachment":[{"href":"https:\/\/engprojects.tcnj.edu\/specificintegratedcircuit16\/wp-json\/wp\/v2\/media?parent=234"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}