Timeline

Semester 1 :

Name	Duration	Actual Start	Finish	Percent Complete
Maintain Website	50 days	8/9/19	10/17/19	30%
Documentation	50 days	8/15/19	10/23/19	50%
Software Architecture	50 days	8/15/19	10/23/19	50%
C UART	50 days	8/19/19	10/25/19	50%
Image and Kernel Storage	3 days	8/28/19	8/30/19	100%
Verification and Debugging	30 days	9/2/19	10/11/19	0%
C Image Loader	35 days	8/15/19	10/2/19	20%
C Image and Kernel Preprocessor	40 days	8/19/19	10/11/19	20%
C UART Master	40 days	8/26/19	10/18/19	50%
Present Data	40 days	8/9/19	10/3/19	30%
Develop Architecture in C Program	40 days	9/2/19	10/25/19	5%
C Image Restitch	50 days	8/26/19	11/1/19	0%
VHDL Data Master	50 days	9/20/19	11/28/19	20%
VHDL Data Master Testing	20 days	9/20/19	10/17/19	0%
Testing and Redesign	20 days	10/15/19	11/11/19	0%
Documentation	70 days	9/5/19	12/11/19	0%

FPGA Design