- September 2, 2015: Design Review #1 Presentation
- September 14, 2015: Finished System Design
- September 24, 2015: Finished Microsoft Project Schedule
- September 25, 2015: Installed Linux for EDA Tool
- October 14, 2015: Design Review #2 Presentation
- November 4, 2015: Finished Code for I2S Input Interface
- November 11, 2015: Finished Code for I2C Interface
- November 18, 2015: Finished Code for I2S Output Interface
- December 2, 2015: Senior Project I Presentation
- December 5, 2015: Senior Project I Final Report Submitted
- December 20, 2015: Started Top-Level Design of Chip
- January 12th, 2016: Finished Top-Level Design of Chip (without register and filter code)
- January 19th, 2016: Started Testbench for Top-Level Design of Chip
- January 26th, 2016: Started Register and I2C Subsystem
- February 10th, 2016: Spring Design Review #1 Presentation
- March 9th, 2016: Finished Code for Entire Chip
- March 16th, 2016: Finished Simulation/Verification on Xilinx
- March 23rd, 2016: Fixed all Synthesis Errors and Warnings.
- March 29th, 2016: Successfully Programmed FPGA
- April 27th, 2016: Filtering Verification Complete
- April 27th, 2016: I2C FPGA Implementation Complete
- May 4th, 2016: Final Presentation
- May 4th, 2016: Celebration of Student Achievement Poster Presentation
- May 11th, 2016: Final Report Submitted
