RTL Design

The register-transfer level (RTL) design is composed of 5 modules. The modules are for the I2C Slave interface (i2c_slave.v), I2S input interface (i2si.v), I2S output interface (i2so.v), register (register.v), and filter (filter.v). All modules are connected in the top-level module named chip.v. All modules have been coded and tested.

  • i2c.v (100%)
  • i2c_deserializer.v (100%)
  • i2c_sequencer.v (100%)
  • i2c_serializer.v (100%)

i2s_in.v (100%): 

  • i2s_in.v (100%)
  • i2si_deserializer.v (100%)
  • i2si_bist_gen.v (100%)
  • i2si_fifo.v (100%)
  • i2si_mux (100%)

i2s_out.v (100%):

  • i2s_out.v (100%)
  • i2so_serializer.v (100%)
  • i2so_fifo.v (100%)

chip_reg.v (100%):

  • register.v (100%)
  • register_trig_gen.v (100%)

filter.v (100%):

  • filter.v (100%)
  • filter_convolution.v (100%)
  • filter_accumulator.v (100%)
  • filter_round_shift_clip.v (100%)